1. Field of the Invention
The present invention relates to a circuit and a method for eliminating bit line leakage current in random access memory devices.
2. Description of the Related Art
Currently, semiconductor memory devices, such as dynamic random access memory (DRAM) devices, are widely used as solid storage media in low-cost digital devices, such as personal computers, cellular phones and personal digital assistants. Generally, a DRAM memory cell, which can store one bit of data, is composed of a transistor and a capacitor. FIG. 1 shows a DRAM memory cell 100 with a transistor 102 and a capacitor 104, wherein one end of the transistor 102 is connected to the capacitor 104, and the other end of the transistor 102 is connected to a bit line BL. The control end of the transistor 102 is connected to a word line WL. The bit of data is stored in the capacitor as electrical charges. Unfortunately, after a certain amount of time, the charges stored in the capacitor 104 are discharged through the substrate or other paths such that the stored data is lost. Accordingly, a periodic refresh operation is required to rewrite the stored data back to the memory cell 100.
To read the data stored in the memory cell 100, a sense amplification technique is applied. Typically, the bit line BL connected to the transistor 102 is connected to a sense amplifier along with another bit line BL′. The sense amplifier determines the data stored in the memory cell 100 by sensing the voltage difference of the voltages on the bit line BL and the bit line BL′. Accordingly, both the bit line BL and the bit line BL′ are pre-charged to a high voltage for the sense amplification technique to be successfully applied. FIG. 2 shows a typical bit line pre-charge circuit applied in a DRAM device. As shown in FIG. 2, the bit line pre-charge circuit 200 comprises a first transistor 202 and a second transistor 204. The first transistor 202 connects a pre-charge voltage VEQ to the bit line BL. The second transistor 204 connects the pre-charge voltage VEQ to the bit line BL′. Both the first transistor 202 and the second transistor 204 are controlled by a pre-charge signal EQD. If the threshold voltages of the first transistor 202 and the second transistor 204 are not equal, the voltages on the bit line BL and the bit line BL′ will not be equal. To overcome this defect, the bit line pre-charge circuit 200 can further comprise a third transistor 206 connecting the bit line BL and the bit line BL′, wherein the third transistor 206 is also controlled by the pre-charge signal EQD.
To reduce power consumption, some DRAM devices can be operated in a self-refresh mode. While operating in a self-refresh mode, the DRAM device cannot be accessed, and a periodic self-refresh operation, performed internally and automatically, is required. FIG. 3 shows a timing diagram of the control signals of a typical DRAM device, wherein the DRAM device is in a self-refresh mode. As shown in FIG. 3, the refresh request is activated periodically, wherein the period is controlled by a timing counter. When a refresh is due, a refresh request is activated, and the refresh operation is performed within the refresh timing window tCBR. When refreshed, the pre-charge signal EQD of the corresponding cell is deactivated, while the pre-charge signal EQD of other cells are kept activated.
Another type of random access memory device, pseudo static random access memory (PSRAM), is a variant of other DRAM devices. A PSRAM device is a DRAM device with built-in refresh and address-control circuitry that allows it to function similarly to a SRAM device. Typically, a PSRAM can be operated in a stand-by mode or an active mode. While operating in an active mode, the PSRAM device can be accessed. However, while operating in a stand-by mode, the PSRAM device cannot be accessed. Both the active mode and the stand-by mode require a periodic refresh operation. FIG. 4 shows a timing diagram of the control signals of a typical PSRAM device. The refresh operation for a PSRAM device operating in a stand-by mode is similar to that of a DRAM device operating in a self-refresh mode. In the active mode, there is a signal ATD (address transition detection) for each access operation. Each ATD pulse interval includes three operations. First, a pre-charge operation for the previously activated address is performed. Second, a refresh operation is performed if a refresh request is activated. Third, a pre-charge operation for the current activated address is performed. As shown in FIG. 4, the pre-charge signal EQD of cells not being refreshed or accessed are kept activated.
However, there are some drawbacks to continuously activating the pre-charge signal EQD. Particularly, there may be bit line leakage currents existing. Referring to FIG. 1, there may be a leakage current between the bit line BL and the word line WL through the inter dielectric. There may be another leakage current between the bit line BL and the word line WL through the gate oxide of the transistor 102. Yet another leakage current could occur between the bit line BL and the P well of the transistor 102 through the contact of the bit line BL. Accordingly, the stand-by current is increased due to the contribution of the bit line leakage currents. A current limiter may be utilized to reduce the bit line leakage currents. However, the bit line leakage currents cannot be fully eliminated. Therefore, there is a need to design a circuit and a method for eliminating bit line leakage current in random access memory devices.